Plltxe.
@plltxe · Post #5883 · 03/12/2026, 12:00 AM
Either my understanding of #Bidi is off, or Jordan Police screw up their Bidi RT: https://twitter.com/Police_Jo/status/2031410145427616135#RTL🐟
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Source channel @olddriverGDstudy · Post #51 · Mar 24
#上头诫#知识 噫吁嚱，呜呼哀哉。佳丽之心， 如渊似海云雾间。前有鬼者心有属，今有上将四人间。心似骄阳深似火，怎当白桓是真心。柳间戏水不得喻，错将弱颜当磐石。今日不见凄鬼之心散步言语现，此时却如千万金石尽如吼头甜。千言万语悬浮脑海间，百转千回纠缠心火炼。上将游戏四水间，怎奈四水通流涧。不得可可不得乖，碧水深潭心坏怜。心知真己不觉少，奈何四水风见消。索向索梁不觉走，回神已在深涧见。深涧云气鬼雾袅，崖山悬顶有佳囡。云烟做红霞，鬼雾做红妆。似是云波似是锦，可文鬼泣是有心。东升日出朝阳起，云散无效鬼泪去。不知南柯曾觉晓，梦里梦外梦惺惺。囡囡心念念，鬼鬼向戚戚。柳七窃窃似潇潇，新年却已入人牢。谁知何时却明晓，涉水不足总深腰。无问无知无所念，有情有景有春宵。尽知尽晓秀哥谣，不管不顾十诫飘。愿此流真做悲景，莫要上头惹人笑。
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@githubtrending · Post #15220 · 10/14/2025, 01:00 PM
#verilog#cocotb#embedded#fpga#iss#risc_v#rtl#verilator#verilog#vpn#vproc#wireguard This project creates an open-source, hardware-based WireGuard VPN using an affordable FPGA board, making fast and secure VPNs more accessible. Unlike slow software VPNs or costly proprietary hardware, this FPGA design runs WireGuard encryption and packet processing at near wire speed without needing a PC host. It uses common tools and languages (SystemVerilog, open-source FPGA tools) and includes a soft CPU for control tasks and hardware logic for data encryption and routing. This means you get a faster, more efficient, and customizable VPN solution that is open and affordable, ideal for learning, development, or deployment in cost-sensitive environments. https://github.com/chili-chips-ba/wireguard-fpga