Plltxe.
@plltxe · Post #5883 · 03/12/2026, 12:00 AM
Either my understanding of #Bidi is off, or Jordan Police screw up their Bidi RT: https://twitter.com/Police_Jo/status/2031410145427616135#RTL🐟
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Source channel @githubtrending · Post #14868 · Jun 26
#typescript#ai_gateway#gateway#generative_ai#hacktoberfest#langchain#llama_index#llmops#llms#openai#prompt_engineering#router The AI Gateway by Portkey lets you connect to over 1600 AI models quickly and securely through one simple API, making it easy to integrate any language, vision, or audio AI model in under two minutes. It ensures fast responses with less than 1ms latency, automatic retries, load balancing, and fallback options to keep your AI apps reliable and scalable. It also offers strong security with role-based access, guardrails, and compliance with standards like SOC2 and GDPR. You can save costs with smart caching and optimize usage without changing your code. This helps you build powerful, cost-effective, and secure AI applications faster and with less hassle. https://github.com/Portkey-AI/gateway
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@githubtrending · Post #15220 · 10/14/2025, 01:00 PM
#verilog#cocotb#embedded#fpga#iss#risc_v#rtl#verilator#verilog#vpn#vproc#wireguard This project creates an open-source, hardware-based WireGuard VPN using an affordable FPGA board, making fast and secure VPNs more accessible. Unlike slow software VPNs or costly proprietary hardware, this FPGA design runs WireGuard encryption and packet processing at near wire speed without needing a PC host. It uses common tools and languages (SystemVerilog, open-source FPGA tools) and includes a soft CPU for control tasks and hardware logic for data encryption and routing. This means you get a faster, more efficient, and customizable VPN solution that is open and affordable, ideal for learning, development, or deployment in cost-sensitive environments. https://github.com/chili-chips-ba/wireguard-fpga