Plltxe.
@plltxe · Post #5883 · 03/12/2026, 12:00 AM
Either my understanding of #Bidi is off, or Jordan Police screw up their Bidi RT: https://twitter.com/Police_Jo/status/2031410145427616135#RTL🐟
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Source channel @githubtrending · Post #15006 · Jul 29
#go#cli#event_driven#event_driven_architecture#queues#serverless#serverless_functions#workflow_engine#workflows Inngest lets you write reliable, long-running background functions called durable workflows that automatically handle retries, scheduling, and state management without needing to manage infrastructure like queues or servers. You write functions in your preferred language using their SDKs, run and test them locally with the Inngest Dev Server, then deploy them on your own infrastructure or Inngest’s platform. It supports complex workflows with steps that retry on failure, concurrency control, and event triggers. This saves you time and effort by simplifying event-driven app development, improving reliability, and scaling automatically without extra setup. It also offers tools for monitoring and managing workflows easily. https://github.com/inngest/inngest
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@githubtrending · Post #15220 · 10/14/2025, 01:00 PM
#verilog#cocotb#embedded#fpga#iss#risc_v#rtl#verilator#verilog#vpn#vproc#wireguard This project creates an open-source, hardware-based WireGuard VPN using an affordable FPGA board, making fast and secure VPNs more accessible. Unlike slow software VPNs or costly proprietary hardware, this FPGA design runs WireGuard encryption and packet processing at near wire speed without needing a PC host. It uses common tools and languages (SystemVerilog, open-source FPGA tools) and includes a soft CPU for control tasks and hardware logic for data encryption and routing. This means you get a faster, more efficient, and customizable VPN solution that is open and affordable, ideal for learning, development, or deployment in cost-sensitive environments. https://github.com/chili-chips-ba/wireguard-fpga