Plltxe.
@plltxe · Post #5883 · 03/12/2026, 12:00 AM
Either my understanding of #Bidi is off, or Jordan Police screw up their Bidi RT: https://twitter.com/Police_Jo/status/2031410145427616135#RTL🐟
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Source channel @githubtrending · Post #15032 · Aug 6
#elixir#debug_adapter_protocol#elixir#language_server#language_server_protocol#lsp ElixirLS is a tool that helps you write and debug Elixir code more easily by providing features like code completion, go-to-definition, inline error reporting, and a powerful debugger that supports breakpoints and step-through debugging. It works with many editors and IDEs through standard protocols, making it flexible to use. It also integrates Dialyzer for static code analysis to catch bugs early and offers a server that helps AI tools understand your code better. Using ElixirLS speeds up development, improves code quality, and makes debugging simpler and more efficient. It supports recent Elixir and OTP versions and can be customized for your project needs. https://github.com/elixir-lsp/elixir-ls
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@githubtrending · Post #15220 · 10/14/2025, 01:00 PM
#verilog#cocotb#embedded#fpga#iss#risc_v#rtl#verilator#verilog#vpn#vproc#wireguard This project creates an open-source, hardware-based WireGuard VPN using an affordable FPGA board, making fast and secure VPNs more accessible. Unlike slow software VPNs or costly proprietary hardware, this FPGA design runs WireGuard encryption and packet processing at near wire speed without needing a PC host. It uses common tools and languages (SystemVerilog, open-source FPGA tools) and includes a soft CPU for control tasks and hardware logic for data encryption and routing. This means you get a faster, more efficient, and customizable VPN solution that is open and affordable, ideal for learning, development, or deployment in cost-sensitive environments. https://github.com/chili-chips-ba/wireguard-fpga