Plltxe.
@plltxe · Post #5883 · 03/12/2026, 12:00 AM
Either my understanding of #Bidi is off, or Jordan Police screw up their Bidi RT: https://twitter.com/Police_Jo/status/2031410145427616135#RTL🐟
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Source channel @githubtrending · Post #15055 · Aug 13
#go#open_telemetry#opentelemetry The OpenTelemetry Collector Contrib is a collection of extra components that extend the core OpenTelemetry Collector, helping you collect, process, and export telemetry data like traces, metrics, and logs from your applications. It supports many features such as filtering sensitive data, batching, retries, and custom processing, which improve security, reliability, and performance of your observability pipeline. You can build custom distributions using these components to fit your needs. This helps you monitor complex systems more easily, reduce costs, and maintain flexibility by supporting many data formats and backends without changing your application code. It is maintained by a community of experts ensuring quality and support. https://github.com/open-telemetry/opentelemetry-collector-contrib
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@githubtrending · Post #15220 · 10/14/2025, 01:00 PM
#verilog#cocotb#embedded#fpga#iss#risc_v#rtl#verilator#verilog#vpn#vproc#wireguard This project creates an open-source, hardware-based WireGuard VPN using an affordable FPGA board, making fast and secure VPNs more accessible. Unlike slow software VPNs or costly proprietary hardware, this FPGA design runs WireGuard encryption and packet processing at near wire speed without needing a PC host. It uses common tools and languages (SystemVerilog, open-source FPGA tools) and includes a soft CPU for control tasks and hardware logic for data encryption and routing. This means you get a faster, more efficient, and customizable VPN solution that is open and affordable, ideal for learning, development, or deployment in cost-sensitive environments. https://github.com/chili-chips-ba/wireguard-fpga