Plltxe.
@plltxe · Post #5883 · 03/12/2026, 12:00 AM
Either my understanding of #Bidi is off, or Jordan Police screw up their Bidi RT: https://twitter.com/Police_Jo/status/2031410145427616135#RTL🐟
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Source channel @githubtrending · Post #15096 · Aug 26
#lua#layout#lua#neovim#neovim_plugin#neovim_ui#nvim#plugin#scratchpad#ui#ux#zen_mode#zenmode The no-neck-pain.nvim plugin for Neovim centers your active editing window by adding empty buffers on each side, creating padding that keeps your focus in the middle of the screen. It works right away without setup, supports multiple tabs, split windows, and integrates with popular file tree and dashboard plugins. You can customize its width, colors, and behavior, and even use the side buffers as scratchpads for notes. This helps reduce neck strain and improves focus, especially on wide monitors, by keeping your code or text centered and easy to read without distractions. https://github.com/shortcuts/no-neck-pain.nvim
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@githubtrending · Post #15220 · 10/14/2025, 01:00 PM
#verilog#cocotb#embedded#fpga#iss#risc_v#rtl#verilator#verilog#vpn#vproc#wireguard This project creates an open-source, hardware-based WireGuard VPN using an affordable FPGA board, making fast and secure VPNs more accessible. Unlike slow software VPNs or costly proprietary hardware, this FPGA design runs WireGuard encryption and packet processing at near wire speed without needing a PC host. It uses common tools and languages (SystemVerilog, open-source FPGA tools) and includes a soft CPU for control tasks and hardware logic for data encryption and routing. This means you get a faster, more efficient, and customizable VPN solution that is open and affordable, ideal for learning, development, or deployment in cost-sensitive environments. https://github.com/chili-chips-ba/wireguard-fpga