#verilog#cocotb#embedded#fpga#iss#risc_v#rtl#verilator#verilog#vpn#vproc#wireguard
This project creates an open-source, hardware-based WireGuard VPN using an affordable FPGA board, making fast and secure VPNs more accessible. Unlike slow software VPNs or costly proprietary hardware, this FPGA design runs WireGuard encryption and packet processing at near wire speed without needing a PC host. It uses common tools and languages (SystemVerilog, open-source FPGA tools) and includes a soft CPU for control tasks and hardware logic for data encryption and routing. This means you get a faster, more efficient, and customizable VPN solution that is open and affordable, ideal for learning, development, or deployment in cost-sensitive environments.
https://github.com/chili-chips-ba/wireguard-fpga
# The standard string repr for dicts is hard to read:
»> my_mapping = {'a': 23, 'b': 42, 'c': 0xc0ffee}
»> my_mapping
{'b': 42, 'c': 12648430. 'a': 23} # 😞
# The "#json" module can do a much better job:
»> import json
»> print(json.dumps(my_mapping, indent=4, sort_keys=True))
{
"a": 23,
"b": 42,
"c": 12648430
}
# Note this only works with dicts containing
# primitive types (check out the "pprint" module):
»> json.dumps({all: 'yup'})
TypeError: keys must be a string
История(12м) как в Альфа-Банке сокращали размер JSON файла, который передается на устройство для работы SDUI. Решением стала шаблонизация для отказа от одинаковых блоков UI с разными данными
#оптимизация#json
¿Que puede hacer este bot?
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