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Source channel @githubtrending · Post #15220 · Oct 14

#verilog#cocotb#embedded#fpga#iss#risc_v#rtl#verilator#verilog#vpn#vproc#wireguard This project creates an open-source, hardware-based WireGuard VPN using an affordable FPGA board, making fast and secure VPNs more accessible. Unlike slow software VPNs or costly proprietary hardware, this FPGA design runs WireGuard encryption and packet processing at near wire speed without needing a PC host. It uses common tools and languages (SystemVerilog, open-source FPGA tools) and includes a soft CPU for control tasks and hardware logic for data encryption and routing. This means you get a faster, more efficient, and customizable VPN solution that is open and affordable, ideal for learning, development, or deployment in cost-sensitive environments. https://github.com/chili-chips-ba/wireguard-fpga

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#verilog #cocotb #embedded #fpga #iss #risc_v #rtl #verilator #vpn #vproc #wireguard

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djangoproject

@djangoproject · Post #132 · 09/01/2016, 02:47 PM

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https://bit.ly/coroutines At Open Source Bridge and #PyGotham in 2015, and at SCALE14x, I demonstrated that you can code a Python 3 #async framework in under an hour. I start the demo by writing a callback-based async framework, built on non-blocking sockets and a simple event loop. Then I adapt the framework to use generator-based #coroutines, which are cleaner than callbacks but still more efficient than threads for async I/O.

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#pygotham #async #coroutines