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Source channel @githubtrending · Post #15220 · Oct 14

#verilog#cocotb#embedded#fpga#iss#risc_v#rtl#verilator#verilog#vpn#vproc#wireguard This project creates an open-source, hardware-based WireGuard VPN using an affordable FPGA board, making fast and secure VPNs more accessible. Unlike slow software VPNs or costly proprietary hardware, this FPGA design runs WireGuard encryption and packet processing at near wire speed without needing a PC host. It uses common tools and languages (SystemVerilog, open-source FPGA tools) and includes a soft CPU for control tasks and hardware logic for data encryption and routing. This means you get a faster, more efficient, and customizable VPN solution that is open and affordable, ideal for learning, development, or deployment in cost-sensitive environments. https://github.com/chili-chips-ba/wireguard-fpga

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djangoproject

@djangoproject · Post #170 · 09/22/2016, 02:27 PM

https://pypi.python.org/pypi/uvloop #uvloop is a fast, drop-in replacement of the built-in #asyncio event loop. uvloop is released under the MIT license. uvloop and asyncio, combined with the power of async/await in Python 3.5, makes it easier than ever to write high-performance #networking code in Python. uvloop makes asyncio fast. In fact, it is at least 2x faster than #nodejs, #gevent, as well as any other Python #asynchronous framework. The performance of uvloop-based asyncio is close to that of Go programs.