@awesomeopensource · Post #147 · 07/25/2018, 02:38 PM
dvc 为机器学习实验设计的版本控制,可以兼容任何git存储库。用于管理实验数据和代码,可以重现实验过程和结果。(视频很有意思) Tags:#machinelearning#versioncontrol#tools Languages:#python
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Source channel @githubtrending · Post #15220 · Oct 14
#verilog#cocotb#embedded#fpga#iss#risc_v#rtl#verilator#verilog#vpn#vproc#wireguard This project creates an open-source, hardware-based WireGuard VPN using an affordable FPGA board, making fast and secure VPNs more accessible. Unlike slow software VPNs or costly proprietary hardware, this FPGA design runs WireGuard encryption and packet processing at near wire speed without needing a PC host. It uses common tools and languages (SystemVerilog, open-source FPGA tools) and includes a soft CPU for control tasks and hardware logic for data encryption and routing. This means you get a faster, more efficient, and customizable VPN solution that is open and affordable, ideal for learning, development, or deployment in cost-sensitive environments. https://github.com/chili-chips-ba/wireguard-fpga
Search: #versioncontrol
@awesomeopensource · Post #147 · 07/25/2018, 02:38 PM
dvc 为机器学习实验设计的版本控制,可以兼容任何git存储库。用于管理实验数据和代码,可以重现实验过程和结果。(视频很有意思) Tags:#machinelearning#versioncontrol#tools Languages:#python