Plltxe.
@plltxe · Post #5883 · 03/12/2026, 12:00 AM
Either my understanding of #Bidi is off, or Jordan Police screw up their Bidi RT: https://twitter.com/Police_Jo/status/2031410145427616135#RTL🐟
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Source channel @githubtrending · Post #15248 · Oct 25
#java#awesome#backend#computer_science#distributed_systems#high_level_design#hld#interview#interview_questions#scalability#system_design You can learn important system design concepts for free, covering topics like scalability, availability, CAP theorem, caching, databases, APIs, microservices, and distributed systems. This resource offers clear explanations, interview preparation guides, and practical design problems from easy to hard, helping you understand how to build reliable, scalable software systems. It also provides links to courses, books, newsletters, and videos to deepen your knowledge. Using these materials can improve your skills for system design interviews and real-world software architecture, making you more confident and effective in designing complex systems. https://github.com/ashishps1/awesome-system-design-resources
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@githubtrending · Post #15220 · 10/14/2025, 01:00 PM
#verilog#cocotb#embedded#fpga#iss#risc_v#rtl#verilator#verilog#vpn#vproc#wireguard This project creates an open-source, hardware-based WireGuard VPN using an affordable FPGA board, making fast and secure VPNs more accessible. Unlike slow software VPNs or costly proprietary hardware, this FPGA design runs WireGuard encryption and packet processing at near wire speed without needing a PC host. It uses common tools and languages (SystemVerilog, open-source FPGA tools) and includes a soft CPU for control tasks and hardware logic for data encryption and routing. This means you get a faster, more efficient, and customizable VPN solution that is open and affordable, ideal for learning, development, or deployment in cost-sensitive environments. https://github.com/chili-chips-ba/wireguard-fpga