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Source channel @pythontelegrambotchannel · Post #75 · Oct 1

Fellow programmers. Happy #hacktoberfest. This event, hosted over here, is about giving back to open source projects. We encourage you all to check it out and make some contributions. We prepared some issues by ourself, they can be found here, but fear not to take on other issues in our repo. If you have any questions, feel free to ask them away in our chats, we are there to help!

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@githubtrending · Post #15220 · 10/14/2025, 01:00 PM

#verilog#cocotb#embedded#fpga#iss#risc_v#rtl#verilator#verilog#vpn#vproc#wireguard This project creates an open-source, hardware-based WireGuard VPN using an affordable FPGA board, making fast and secure VPNs more accessible. Unlike slow software VPNs or costly proprietary hardware, this FPGA design runs WireGuard encryption and packet processing at near wire speed without needing a PC host. It uses common tools and languages (SystemVerilog, open-source FPGA tools) and includes a soft CPU for control tasks and hardware logic for data encryption and routing. This means you get a faster, more efficient, and customizable VPN solution that is open and affordable, ideal for learning, development, or deployment in cost-sensitive environments. https://github.com/chili-chips-ba/wireguard-fpga