Plltxe.
@plltxe · Post #5883 · 03/12/2026, 12:00 AM
Either my understanding of #Bidi is off, or Jordan Police screw up their Bidi RT: https://twitter.com/Police_Jo/status/2031410145427616135#RTL🐟
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Source channel @pythontelegrambotchannel · Post #89 · Oct 7
The v13 release is not just a release either, it is also our official announcement of participation in the annual #hacktoberfest. 💻🥨 We know that we're a few days late to the party, but v13 had to get ready before. 😉 This year, the fest is opt-in for projects and we definitely want to opt into taking part in this great event! If you ever thought about starting coding or giving back to your favourite open source repositories, now is the time! Head over to the hacktoberfest website to learn more about it. We already prepared some issues on our repositories and aim towards opening more issues for starters, but feel free to begin a hunt for improvements and fixes by yourself!
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@githubtrending · Post #15220 · 10/14/2025, 01:00 PM
#verilog#cocotb#embedded#fpga#iss#risc_v#rtl#verilator#verilog#vpn#vproc#wireguard This project creates an open-source, hardware-based WireGuard VPN using an affordable FPGA board, making fast and secure VPNs more accessible. Unlike slow software VPNs or costly proprietary hardware, this FPGA design runs WireGuard encryption and packet processing at near wire speed without needing a PC host. It uses common tools and languages (SystemVerilog, open-source FPGA tools) and includes a soft CPU for control tasks and hardware logic for data encryption and routing. This means you get a faster, more efficient, and customizable VPN solution that is open and affordable, ideal for learning, development, or deployment in cost-sensitive environments. https://github.com/chili-chips-ba/wireguard-fpga