@plltxe · Post #5883 · 12/03/2026, 00:00
Either my understanding of #Bidi is off, or Jordan Police screw up their Bidi RT: https://twitter.com/Police_Jo/status/2031410145427616135#RTL🐟
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Canale sorgente @WritingWay · Post #1306 · 5 apr
SCRIVERE BENE? ✍️📖 ➡️➡️➡️VERIFICA DI RISPETTARE ALMENO QUESTE 10 REGOLE ⬅️⬅️⬅️ ✍🏻 La buona scrittura si compone di due aspetti, uno oggettivo e uno soggettivo. Contano le regole, gli accorgimenti tecnici ma conta anche l'attitudine. #audiowriting#podcast#scrittura 🎧In questo audio elenco e commento 10 regole: verifica se le applichi nella tua scrittura. @writingway 🙌Se pensi che questo audio possa interessare ad altri, inoltralo cliccando sulla freccia a destra.
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@plltxe · Post #5883 · 12/03/2026, 00:00
Either my understanding of #Bidi is off, or Jordan Police screw up their Bidi RT: https://twitter.com/Police_Jo/status/2031410145427616135#RTL🐟
@githubtrending · Post #15220 · 14/10/2025, 13:00
#verilog#cocotb#embedded#fpga#iss#risc_v#rtl#verilator#verilog#vpn#vproc#wireguard This project creates an open-source, hardware-based WireGuard VPN using an affordable FPGA board, making fast and secure VPNs more accessible. Unlike slow software VPNs or costly proprietary hardware, this FPGA design runs WireGuard encryption and packet processing at near wire speed without needing a PC host. It uses common tools and languages (SystemVerilog, open-source FPGA tools) and includes a soft CPU for control tasks and hardware logic for data encryption and routing. This means you get a faster, more efficient, and customizable VPN solution that is open and affordable, ideal for learning, development, or deployment in cost-sensitive environments. https://github.com/chili-chips-ba/wireguard-fpga