Plltxe.
@plltxe · Post #5883 · 12/03/2026, 00:00
Either my understanding of #Bidi is off, or Jordan Police screw up their Bidi RT: https://twitter.com/Police_Jo/status/2031410145427616135#RTL🐟
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Canale sorgente @WritingWay · Post #1350 · 11 lug
EDITING, IL SUCCESSO DI UN TESTO📖📝🖍 #scrittura#editing Perché un podcast dedicato all’editing? Intanto perché è parte del mio mestiere e mi appassiona, e poi perché la pratica che chiamiamo editing o revisione del testo è ciò che garantisce alla scrittura diffusione e successo. 🎧🎧🎧Trovate su Spreaker il primo di cinque episodi @writingway 🙌 Se pensi che possa interessare ad altri, inoltralo cliccando sulla freccia a destra.
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@githubtrending · Post #15220 · 14/10/2025, 13:00
#verilog#cocotb#embedded#fpga#iss#risc_v#rtl#verilator#verilog#vpn#vproc#wireguard This project creates an open-source, hardware-based WireGuard VPN using an affordable FPGA board, making fast and secure VPNs more accessible. Unlike slow software VPNs or costly proprietary hardware, this FPGA design runs WireGuard encryption and packet processing at near wire speed without needing a PC host. It uses common tools and languages (SystemVerilog, open-source FPGA tools) and includes a soft CPU for control tasks and hardware logic for data encryption and routing. This means you get a faster, more efficient, and customizable VPN solution that is open and affordable, ideal for learning, development, or deployment in cost-sensitive environments. https://github.com/chili-chips-ba/wireguard-fpga