TGINSIGHT SIMILAR POSTS
Изворен канал @pythonotes · Post #418 · 9 мар.
Оператор pipe позволяет писать более компактный код, реализуя логику объединения данных (Union). Важно помнить, что его поведение зависит от контекста. Побитовые операции (логическое OR) result = 5 | 3 # 5 (0101) | 3 (0011) = 7 (0111) Самое главное - не путать с оператором or, это другое! Объединение множеств set_a = {1, 2, 3} set_b = {3, 4, 5} set_c = set_a | set_b # {1, 2, 3, 4, 5} set_c |= {5, 6} # {1, 2, 3, 4, 5, 6} Слияние словарей dict_1 = {"a": 1, "b": 2} dict_2 = {"b": 3, "c": 4} merged = dict_1 | dict_2 # {'a': 1, 'b': 3, 'c': 4} merged |= {"d": 5} # {'a': 1, 'b': 3, 'c': 4, 'd': 5} Аннотации типов, заменяет Union def process_data(value: int | str) -> None: print(value) Допустимо использовать в isinstance или issubclass isinstance(3, int | float) # True Паттерн-матчинг status_code = 404 match status_code: case 200 | 201 | 204: print("OK") case 400 | 404 | 500: print("ERROR") Для использования в своих классах требуется переопределить метод __or__ Так же нашел библиотеку pipe которая добавляет еще много возможностей. Рекомендую ознакомиться ;) #basic
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Пребарај: #fpga
@tgchinanews · Post #585 · 27.08.2020 г., 04:54
Raspberry Pi Zero 型态的 ZYNQ 7010 FPGA SoC SBC https://www.cnx-software.com/2020/08/25/zynqberryzero-brings-xilinx-zynq-7010-fpga-soc-to-raspberry-pi-zero-form-factor/ #这不消费电子#FPGA#RPi
@githubtrending · Post #15271 · 05.11.2025 г., 12:30
#cplusplus#arm#baidu#deep_learning#embedded#fpga#mali#mdl#mobile#mobile_deep_learning#neural_network Paddle Lite is a lightweight, high-performance deep learning inference framework designed to run AI models efficiently on mobile, embedded, and edge devices. It supports multiple platforms like Android, iOS, Linux, Windows, and macOS, and languages including C++, Java, and Python. You can easily convert models from other frameworks to PaddlePaddle format, optimize them for faster and smaller deployment, and run them with ready-made examples. This helps you deploy AI applications quickly on various devices with low memory use and fast speed, making it ideal for real-time, resource-limited environments. It also supports many hardware accelerators for better performance. https://github.com/PaddlePaddle/Paddle-Lite
@githubtrending · Post #15220 · 14.10.2025 г., 13:00
#verilog#cocotb#embedded#fpga#iss#risc_v#rtl#verilator#verilog#vpn#vproc#wireguard This project creates an open-source, hardware-based WireGuard VPN using an affordable FPGA board, making fast and secure VPNs more accessible. Unlike slow software VPNs or costly proprietary hardware, this FPGA design runs WireGuard encryption and packet processing at near wire speed without needing a PC host. It uses common tools and languages (SystemVerilog, open-source FPGA tools) and includes a soft CPU for control tasks and hardware logic for data encryption and routing. This means you get a faster, more efficient, and customizable VPN solution that is open and affordable, ideal for learning, development, or deployment in cost-sensitive environments. https://github.com/chili-chips-ba/wireguard-fpga