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Kanal tas-sors @linuxgram · Post #17841 · Fra 19

📰 AI Helped Uncover A "50-80x Improvement" For Linux's IO_uring Linux block maintainer and IO_uring lead developer Jens Axboe recently was debugging some slowdowns in the AHCI/SCSI code with IO_uring usage. When turning to Claude AI to help in sorting through the issue, patches were devised that can deliver up to a "literally yield a 50-80x improvement on the io_uring side for idle systems." The code is on its way to the Linux kernel... 🔗 Source: https://www.phoronix.com/news/AI-50-80x-IO-uring #linux#kernel

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@githubtrending · Post #15220 · 14/10/2025 13:00

#verilog#cocotb#embedded#fpga#iss#risc_v#rtl#verilator#verilog#vpn#vproc#wireguard This project creates an open-source, hardware-based WireGuard VPN using an affordable FPGA board, making fast and secure VPNs more accessible. Unlike slow software VPNs or costly proprietary hardware, this FPGA design runs WireGuard encryption and packet processing at near wire speed without needing a PC host. It uses common tools and languages (SystemVerilog, open-source FPGA tools) and includes a soft CPU for control tasks and hardware logic for data encryption and routing. This means you get a faster, more efficient, and customizable VPN solution that is open and affordable, ideal for learning, development, or deployment in cost-sensitive environments. https://github.com/chili-chips-ba/wireguard-fpga