@tgchinanews · Post #585 · 2020/08/27 04:54
Raspberry Pi Zero 型态的 ZYNQ 7010 FPGA SoC SBC https://www.cnx-software.com/2020/08/25/zynqberryzero-brings-xilinx-zynq-7010-fpga-soc-to-raspberry-pi-zero-form-factor/ #这不消费电子#FPGA#RPi
#青龙更新 青龙 v2.18.1 更新说明 青龙 v2.18.1 发布!本次更新优化功能并修复问题: • 新增功能:内置 QLAPI 增加环境变量和系统通知 API。 • 调整:移除 nedb 和 sentry,不再支持 2.10.x 版本自动迁移。 • 修复:多语言翻译问题改进。 更新方法: • 面板更新:系统设置 -> 其他设置 -> 检查更新 • 容器内更新:执行 ql update • Debian 用户:直接同步更新。 • 宿主机更新:运行命令 docker run --rm -v /var/run/docker.sock:/var/run/docker.sock containrrr/watchtower -cR <容器名> 版本镜像: • 正式版:whyour/qinglong:latest • Python3.10 正式版:whyour/qinglong:python3.10 • Debian 版:whyour/qinglong:debian • Python3.10 Debian 版:whyour/qinglong:debian-python3.10 • NPM 安装:npm i -g @whyour/qinglong 📢 群聊: @TossLab 🎈 频道: @TossLabChannel ❗️ ❗️ ❗️ ❗️ ❗️ ❗️ ❗️ ❗️ 🔘折腾系列频道 - 全面介绍 🔘境外离岸银行教程合集目录 🔘折腾实验室优质Github项目合集
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@tgchinanews · Post #585 · 2020/08/27 04:54
Raspberry Pi Zero 型态的 ZYNQ 7010 FPGA SoC SBC https://www.cnx-software.com/2020/08/25/zynqberryzero-brings-xilinx-zynq-7010-fpga-soc-to-raspberry-pi-zero-form-factor/ #这不消费电子#FPGA#RPi
@githubtrending · Post #15271 · 2025/11/05 12:30
#cplusplus#arm#baidu#deep_learning#embedded#fpga#mali#mdl#mobile#mobile_deep_learning#neural_network Paddle Lite is a lightweight, high-performance deep learning inference framework designed to run AI models efficiently on mobile, embedded, and edge devices. It supports multiple platforms like Android, iOS, Linux, Windows, and macOS, and languages including C++, Java, and Python. You can easily convert models from other frameworks to PaddlePaddle format, optimize them for faster and smaller deployment, and run them with ready-made examples. This helps you deploy AI applications quickly on various devices with low memory use and fast speed, making it ideal for real-time, resource-limited environments. It also supports many hardware accelerators for better performance. https://github.com/PaddlePaddle/Paddle-Lite
@githubtrending · Post #15220 · 2025/10/14 13:00
#verilog#cocotb#embedded#fpga#iss#risc_v#rtl#verilator#verilog#vpn#vproc#wireguard This project creates an open-source, hardware-based WireGuard VPN using an affordable FPGA board, making fast and secure VPNs more accessible. Unlike slow software VPNs or costly proprietary hardware, this FPGA design runs WireGuard encryption and packet processing at near wire speed without needing a PC host. It uses common tools and languages (SystemVerilog, open-source FPGA tools) and includes a soft CPU for control tasks and hardware logic for data encryption and routing. This means you get a faster, more efficient, and customizable VPN solution that is open and affordable, ideal for learning, development, or deployment in cost-sensitive environments. https://github.com/chili-chips-ba/wireguard-fpga