Either my understanding of #Bidi is off, or Jordan Police screw up their Bidi RT: https://twitter.com/Police_Jo/status/2031410145427616135#RTL🐟
TGTGInsighttelegram intelligenceLIVE / telegram public index
#稀土掘金 适配新版完了，url 多了个验证，所以要多抓一个 打开 F12，手动签到完之后，找到 https://api.juejin.cn/growth_api/v1/check_in 然后获取 url 的 uuid=123456&spider=0&msToken=xxxxxx&a_bogus=xxxxxx 填写示例： export JUEJIN_COOKIE='xxxxx#uuid=123456&spider=0&msToken=xxxxxx&a_bogus=xxxxxx' 用 # 分开
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@githubtrending · Post #15220 · 2025/10/14 13:00
#verilog#cocotb#embedded#fpga#iss#risc_v#rtl#verilator#verilog#vpn#vproc#wireguard This project creates an open-source, hardware-based WireGuard VPN using an affordable FPGA board, making fast and secure VPNs more accessible. Unlike slow software VPNs or costly proprietary hardware, this FPGA design runs WireGuard encryption and packet processing at near wire speed without needing a PC host. It uses common tools and languages (SystemVerilog, open-source FPGA tools) and includes a soft CPU for control tasks and hardware logic for data encryption and routing. This means you get a faster, more efficient, and customizable VPN solution that is open and affordable, ideal for learning, development, or deployment in cost-sensitive environments. https://github.com/chili-chips-ba/wireguard-fpga