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Source channel @githubredteam · Post #82601 · 5月3日

🚨 GitHub 监控消息提醒 🚨发现关键词:#漏洞#利用#分析 📦项目名称:cve-llm-kg 👤项目作者:nantangqiuweiwan 🛠开发语言: Python ⭐Star数量: 1 | 🍴Fork数量: 0 📅更新时间: 2026-05-03 09:58:37 📝项目描述: 基于 LLM 的 CVE 漏洞知识图谱构建与分析:针对网络协议相关的 CVE 漏洞,设计 Prompt,利用大语言模型作为“智能解析器”,从非结构化的 CVE 描述中自动抽取关键实体和关系。将抽取出的实体和关系导入图数据库,构建一个可视化的物联网漏洞知识图谱。 🔗点击访问项目地址

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@githubtrending · Post #15220 · 2025/10/14 13:00

#verilog#cocotb#embedded#fpga#iss#risc_v#rtl#verilator#verilog#vpn#vproc#wireguard This project creates an open-source, hardware-based WireGuard VPN using an affordable FPGA board, making fast and secure VPNs more accessible. Unlike slow software VPNs or costly proprietary hardware, this FPGA design runs WireGuard encryption and packet processing at near wire speed without needing a PC host. It uses common tools and languages (SystemVerilog, open-source FPGA tools) and includes a soft CPU for control tasks and hardware logic for data encryption and routing. This means you get a faster, more efficient, and customizable VPN solution that is open and affordable, ideal for learning, development, or deployment in cost-sensitive environments. https://github.com/chili-chips-ba/wireguard-fpga