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Source channel @githubtrending · Post #15616 · Apr 15

#cplusplus#hap#mid_360#ros#ros2 Livox ROS Driver 2 connects your Livox LiDARs like HAP and Mid360 to ROS (Noetic) or ROS2 (Foxy/Humble/Jazzy) on matching Ubuntu versions. Clone the repo in a workspace/src folder, build Livox-SDK2, then run ./build.sh with your ROS version, and launch with roslaunch or ros2 launch files from launch_ROS1/ROS2 folders—edit JSON configs for IP, ports, frequency (up to 100Hz), and formats. This lets you quickly test and visualize point clouds in RViz for robotics development, saving time on setup and debugging. https://github.com/Livox-SDK/livox_ros_driver2

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@tgchinanews · Post #585 · 08/27/2020, 04:54 AM

Raspberry Pi Zero 型态的 ZYNQ 7010 FPGA SoC SBC https://www.cnx-software.com/2020/08/25/zynqberryzero-brings-xilinx-zynq-7010-fpga-soc-to-raspberry-pi-zero-form-factor/ #这不消费电子#FPGA#RPi

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@githubtrending · Post #15271 · 11/05/2025, 12:30 PM

#cplusplus#arm#baidu#deep_learning#embedded#fpga#mali#mdl#mobile#mobile_deep_learning#neural_network Paddle Lite is a lightweight, high-performance deep learning inference framework designed to run AI models efficiently on mobile, embedded, and edge devices. It supports multiple platforms like Android, iOS, Linux, Windows, and macOS, and languages including C++, Java, and Python. You can easily convert models from other frameworks to PaddlePaddle format, optimize them for faster and smaller deployment, and run them with ready-made examples. This helps you deploy AI applications quickly on various devices with low memory use and fast speed, making it ideal for real-time, resource-limited environments. It also supports many hardware accelerators for better performance. https://github.com/PaddlePaddle/Paddle-Lite

GitHub Trends

@githubtrending · Post #15220 · 10/14/2025, 01:00 PM

#verilog#cocotb#embedded#fpga#iss#risc_v#rtl#verilator#verilog#vpn#vproc#wireguard This project creates an open-source, hardware-based WireGuard VPN using an affordable FPGA board, making fast and secure VPNs more accessible. Unlike slow software VPNs or costly proprietary hardware, this FPGA design runs WireGuard encryption and packet processing at near wire speed without needing a PC host. It uses common tools and languages (SystemVerilog, open-source FPGA tools) and includes a soft CPU for control tasks and hardware logic for data encryption and routing. This means you get a faster, more efficient, and customizable VPN solution that is open and affordable, ideal for learning, development, or deployment in cost-sensitive environments. https://github.com/chili-chips-ba/wireguard-fpga